Item Type |
Article |
ID |
|
Preview |
Image |
|
Caption |
|
|
Full text |
KAKEN_26420318seika.pdf
Type |
:application/pdf |
Download
|
Size |
:1.0 MB
|
Last updated |
:Sep 21, 2017 |
Downloads |
: 524 |
Total downloads since Sep 21, 2017 : 524
|
|
Release Date |
|
Title |
Title |
人工シナプス用多チャンネル膜電位固定LSIの実現
|
Kana |
ジンコウ シナプスヨウ タチャンネルマク デンイ コテイ LSI ノ ジツゲン
|
Romanization |
Jinko shinapusuyo tachannerumaku deni kotei LSI no jitsugen
|
|
Other Title |
Title |
Design of multichannel LSI system for artificial synapse based on whole cell voltage clamp method
|
Kana |
|
Romanization |
|
|
Creator |
Name |
中野, 誠彦
|
Kana |
ナカノ, ノブヒコ
|
Romanization |
Nakano, Nobuhiko
|
Affiliation |
慶應義塾大学・理工学部・准教授
|
Affiliation (Translated) |
|
Role |
Research team head
|
Link |
科研費研究者番号 : 40286638
|
Name |
樫村, 吉晃
|
Kana |
カシムラ, ヨシアキ
|
Romanization |
Kashimura, Yoshiaki
|
Affiliation |
日本電信電話株式会社NTT物性化学基礎研究所・機能物質科学研究部・主任研究員
|
Affiliation (Translated) |
|
Role |
Research team member
|
Link |
科研費研究者番号 : 90393751
|
|
Edition |
|
Place |
|
Publisher |
|
Date |
Issued (from:yyyy) |
2017
|
Issued (to:yyyy) |
|
Created (yyyy-mm-dd) |
|
Updated (yyyy-mm-dd) |
|
Captured (yyyy-mm-dd) |
|
|
Physical description |
|
Source Title |
Name |
科学研究費補助金研究成果報告書
|
Name (Translated) |
|
Volume |
|
Issue |
|
Year |
2016
|
Month |
|
Start page |
|
End page |
|
|
ISSN |
|
ISBN |
|
DOI |
|
URI |
|
JaLCDOI |
|
NII Article ID |
|
Ichushi ID |
|
Other ID |
|
Doctoral dissertation |
Dissertation Number |
|
Date of granted |
|
Degree name |
|
Degree grantor |
|
|
Abstract |
本研究では神経細胞と直接やりとりを行う人工シナプス実現に向けてLSI設計を行った。膜電位固定法と呼ばれる手法を再現しており, 細胞のイオンチャネルを通過する電流を取得するものである。高倍率の電流電圧変換器を設計し高抵抗を標準CMOSプロセスを用いてチップ上に作成し信号取得に必要な周波数帯域を確保しながら低雑音かつ高増幅率を実現した。さらにシステムを多チャネル化し5mm角チップに16チャネルシステムを実装した。
In this study, we designed LSI for realizing artificial synapse which communicate directly with nerve cells. It reproduces the method called whole cell voltage clamp method and acquires the current passing through the ion channel of the cell. LSI chip was designed with high magnification current to voltage converter using high resistance on the chip by standard CMOS process to realize low noise and high amplification ratio while realize the frequency bandwidth required for signal acquisition. The 16-channel system was implemented on 5 mm x 5 mm size chip.
|
|
Table of contents |
|
Keyword |
|
NDC |
|
Note |
研究種目 : 基盤研究(C)(一般)
研究期間 : 2014~2016
課題番号 : 26420318
研究分野 : 集積回路設計
|
|
Language |
|
Type of resource |
|
Genre |
|
Text version |
|
Related DOI |
|
Access conditions |
|
Last modified date |
|
Creation date |
|
Registerd by |
|
History |
|
Index |
|
Related to |
|